With the significant growth of the hardware and software design complexity, the modern SoC development cycle is also greatly increased. Using the traditional register transfer level (RTL) design methodology is too time-consuming especially for the modern SoC design which needs a high integration of software and hardware. Therefore, it has become the inevitable trend to adopt the electronic system level (ESL) design methodology to improve the productivity of modern system design. To further reuse the developed ESL model, a high-level synthesis tool is widely used to change the ESL model into the RTL.
Power consumption has always been a crucial problem of a chip due to the increasing hardware complexity and operating frequency. Currently, many researches point out that the minimizing power consumption in ESL can have better power gain than in the RTL or gate level. According to the report of the International Technology Roadmap for Semiconductor (ITRS) in 2009, 50% power saving will be achieved in ESL in 2011; and it will go up to 80% in 2015 while we minimizing power consumption in ESL. In the ESL, the transaction level (TL) has the widest range of application. Therefore, it is necessary to estimate the power in an earlier stage of design and at a higher design level—transaction level. However, there are many difficulties for the designers to make estimation and analysis of the power consumption from the TL in the early stage of design. The designers might not effectively provision and plan characteristic extractor in the TL of design.